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2M x 32-Bit Dynamic RAM Module (Hyper Page Mode - EDO Version)
HYM 322005S/GS-50/-60
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SIMM modules with 2 097 152 words by 32-bit organization for PC main memory application Fast access and cycle time 50 ns access time 84 ns cycle time (-50 version) 60 ns access time 104 ns cycle time (-60 version) Hyper page mode - EDO capability with 20 ns cycle time (-50 version) 25 ns cycle time (-60 version) Single + 5 V ( 10 %) supply Low power dissipation max. 2200 mW active (-50 version) max. 1980 mW active (-60 version) CMOS - 22 mW standby TTL - 44 mW standby CAS-before-RAS refresh, RAS-only-refresh, Hidden refresh 4 decoupling capacitors mounted on substrate All inputs, outputs and clock fully TTL compatible 72 pin Single in-Line Memory Module Utilizes four 1M x 16 -DRAMs in SOJ-42 packages 1024 refresh cycles / 16 ms Optimized for use in byte-write non-parity applications Tin-Lead contact pad HYM 322005S Gold-Lead contact pad HYM 322005GS single sided module with 20.32 mm (800 mil) height
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Semiconductor Group
1
9.96
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
The HYM 322005S/GS-50/-60 is a 8 MByte EDO - DRAM module organized as 2 097 152 words by 32-bit in a 72-pin single-in-line package comprising four HYB 5118160BSJ 1M x 16 EDO - DRAMs in 400 mil wide SOJ-packages mounted together with four 0.2 F ceramic decoupling capacitors on a PC board. Each HYB 5118165BSJ is described in the data sheet and is fully electrically tested and processed according to Siemens standard quality procedure prior to module assembly. After assembly onto the board, a further set of electrical tests is performed. The speed of the module can be detected by the use presence detect pins. The common I/O feature on the HYM 322005S/GS-50/-60 dictates the use of early write cycles. Ordering Information Type HYM 322005S-50 HYM 322005S-60 HYM 322005GS-50 HYM 322005GS-60 Ordering Code Q67100-Q2066 Q67100-Q2067 Q67100-Q2068 Q67100-Q2069 Package L-SIM-72-10 L-SIM-72-10 L-SIM-72-10 L-SIM-72-10 Descriptions EDO - DRAM module (access time 50 ns) EDO - DRAM module (access time 60 ns) EDO - DRAM module (access time 50 ns) EDO - DRAM module (access time 60 ns)
Semiconductor Group
2
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
Pin Names
VSS DQ16 DQ17 DQ18 DQ19 N.C. A1 A3 A5 N.C. DQ20 DQ21 DQ22 DQ23 N.C. A8 RAS3 N.C. 1 DQ0 2 3 DQ1 4 5 DQ2 6 7 DQ3 8 9 VCC 10 11 A0 12 13 A2 14 15 A4 16 17 A6 18 19 DQ4 20 21 DQ5 22 23 DQ6 24 25 DQ7 26 27 A7 28 29 VCC 30 31 A9 32 33 RAS2 34 35 N.C. 36
A0-A9 DQ0-DQ31 CAS0 - CAS3 RAS0 - RAS3 WE
Address Inputs Data Input/Output Column Address Strobe Row Address Strobe Read/Write Input Power (+ 5 V) Ground Presence Detect Pin No Connection
VCC VSS
PD N.C.
N.C. VSS CAS2 CAS1 RAS1 WE DQ8 DQ9 DQ10 DQ11 DQ12 VCC DQ13 DQ14 DQ15 PD0 PD2 N.C.
37 39 41 43 45 47 49 51 53 55 57 59 61 63 65 67 69 71
N.C. 38 CAS0 40 CAS3 42 RAS0 44 N.C. 46 N.C. 48 DQ24 50 DQ25 52 DQ26 54 DQ27 56 DQ28 58 DQ29 60 DQ30 62 DQ31 64 N.C. 66 PD1 68 PD3 70 VSS 72
Presence Detect Pins -50 PD0 PD1 PD2 PD3 N.C. N.C. -60 N.C. N.C N.C. N.C.
VSS VSS
Pin Configuration
Semiconductor Group
3
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
RAS0 CAS0 CAS1
RAS1
UCAS LCAS RAS DQ0-DQ7 DQ8-DQ15 I/O1-I/O8
UCAS LCAS RAS I/O1-I/O8
I/O9-I/O16 OE
I/O9-I/O16 OE
D1
D3
RAS2 CAS2 CAS3
RAS3
UCAS LCAS RAS DQ16-DQ23 DQ24-DQ31 I/O1-I/O8
UCAS LCAS RAS I/O1-I/O8
I/O9-I/O16 OE
I/O9-I/O16 OE
D2
D4
A0 - A9 WE VCC VSS C1 -C4
D1 - D4 D1 - D4
Block Diagram
Semiconductor Group
4
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
Absolute Maximum Ratings Operating temperature range ......................................................................................... 0 to + 70 C Storage temperature range...................................................................................... - 55 to + 125 C Input/output voltage ........................................................................................................ - 1 to + 7 V Power supply voltage...................................................................................................... - 1 to + 7 V Power dissipation................................................................................................................... 2.52 W Data out current (short circuit) ................................................................................................ 50 mA Note: Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. Exposure to absolute maximum rating conditions for extended periods may affect device reliability.
DC Characteristics TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %; tT = 2 ns Parameter Input high voltage Input low voltage Output high voltage (IOUT = - 5 mA) Output low voltage (IOUT = 4.2 mA) Input leakage current (0 V VIH Vcc + 0.3V, all other pins = 0 V) Output leakage current (DO is disabled, 0 V VOUT Vcc + 0.3V) Average VCC supply current: -50 ns version -60 ns version (RAS, CAS, address cycling: tRC = tRC min.) Standby VCC supply current (RAS = CAS = VIH) Average VCC supply current, during RAS-only refresh cycles: -50 ns version -60 ns version (RAS cycling, CAS = VI,H, tRC = tRC min.) Symbol Limit Values min. max. Vcc+0.5 0.8 - 0.4 10 10 2.4 - 0.5 2.4 - - 10 - 10 Unit Test Condition V V V V A A
1) 1) 1) 1) 1)
VIH VIL VOH VOL II(L) IO(L) ICC1
1)
- -
400 360 8
mA mA mA
2) 3) 4) 2) 3) 4)
ICC2 ICC3
-
-
- -
400 360
mA mA
2) 4) 2) 4)
Average VCC supply current,during hyper page ICC4 mode (EDO): -50 ns version -60 ns version (RAS = VIL, CAS, address cycling: (tHPC = tHPC min.)
- -
180 150
mA mA
2) 3) 4) 2) 3) 4)
Semiconductor Group
5
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
DC Characteristics (cont' d) TA = 0 to 70 C, VSS = 0 V, VCC = 5 V 10 %; tT = 2 ns Parameter Standby VCC supply current (RAS = CAS = VCC - 0.2 V) Average VCC supply current, during CASbefore-RAS refresh mode: -50 ns version -60 ns version (RAS, CAS cycling: tRC = tRC min.) Symbol Limit Values min. max. 4 - Unit Test Condition mA
1)
ICC5 ICC6
- -
400 360
mA mA
2) 4) 2) 4)
Capacitance TA = 0 to 70 C; VCC = 5 V 10 %; f = 1 MHz Parameter Input capacitance (A0 to A9) Input capacitance (RAS0, RAS2) Input capacitance (CAS0-CAS3) Input capacitance (WE) I/O capacitance (DQ0-DQ31) Symbol min. Limit Values max. 35 20 20 35 25 pF pF pF pF pF - - - - - Unit
CI1 CI2 CI3 CI4 CIO1
Semiconductor Group
6
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
AC Characteristics 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
Limit Values -50 min. max. min. -60 max.
Unit
Note
common parameters
Random read or write cycle time RAS precharge time RAS pulse width CAS pulse width Row address setup time Row address hold time Column address setup time Column address hold time RAS to CAS delay time RAS to column address delay time RAS hold time CAS hold time CAS to RAS precharge time Transition time (rise and fall) Refresh period tRC tRP tRAS tCAS tASR tRAH tASC tCAH tRCD tRAD tRSH tCSH tCRP tT tREF 84 30 50 8 0 8 0 8 12 10 13 40 5 1 - - 50 16 - - 10k 10k - - - - 37 25 104 40 60 10 0 10 0 10 14 12 15 50 5 1 - - - 10k 10k - - - - 45 30 - - - 50 16 ns ns ns ns ns ns ns ns ns ns ns ns ns ns ms 7
Read Cycle
Access time from RAS Access time from CAS Access time from column address Column address to RAS lead time Read command setup time Read command hold time Read command hold time referenced to RAS CAS to output in low-Z Output buffer turn-off delay tRAC tCAC tAA tRAL tRCS tRCH tRRH tCLZ tOFF - - - 25 0 0 0 0 0 50 13 25 - - - - - 13 - - - 30 0 0 0 0 0 60 15 30 - - - - - 15 ns ns ns ns ns ns ns ns ns 11 11 8 12 8, 9 8, 9 8,10
Semiconductor Group
7
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
AC Characteristics (cont' d) 5)6) TA = 0 to 70 C,VCC = 5 V 10 %, tT = 2 ns Parameter
Symbol
Limit Values -50 min. max. - - - - - - - min. 10 10 0 15 15 0 10 -60 max. - - - - - - -
Unit
Note
Early Write Cycle
Write command hold time Write command pulse width Write command setup time Write command to RAS lead time Write command to CAS lead time Data setup time Data hold time tWCH tWP tWCS tRWL tCWL tDS tDH 8 8 0 13 13 0 8 ns ns ns ns ns ns ns 14 14 13
Hyper Page Mode (EDO) Cycle
Hyper page mode (EDO) cycle time CAS precharge time Access time from CAS precharge Output data hold time RAS pulse width in hyper page mode CAS precharge to RAS Delay tHPC tCP tCPA tCOH tRAS tRHCP 20 8 - 5 50 27 - - 27 - 200k - 25 10 - 5 60 32 - - 32 - 200k - ns ns ns ns ns ns 7
CAS before RAS Refresh Cycle
CAS setup time CAS hold time RAS to CAS precharge time Write to RAS precharge time Write hold time referenced to RAS tCSR tCHR tRPC tWRP tWRH 10 10 5 10 10 - - - - - 10 10 5 10 10 - - - - - ns ns ns ns ns
Semiconductor Group
8
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
Notes
1) All voltages are referenced to VSS. Vil may undershoot to -2.0 V for pulse width of less than or equal to 4 ns. Pulse width is measured at 50% points with amplitude measured peak to the DC reference. 2) ICC1, ICC3, ICC4 and ICC6 depend on cycle rate. 3) ICC1 and ICC4 depend on output loading. Specified values are obtained with the output open. 4) Address can be changed once or less while RAS = Vil. In case of ICC4 it can be changed once or less during a hyper page mode (EDO) cycle. 5) An initial pause of 200 s is required after power-up followed by 8 RAS cycles of which at least one cycle has to be a refresh cycle, before proper device operation is achieved. In case of using the internal refresh counter, a minimum of 8 CAS-before-RAS initialization cycles instead of 8 RAS cycles are required. 6) AC measurements assume
tT = 2 ns.
7) VIH (min.) and VIL (max.) are reference levels for measuring timing of input signals. Transition times are also measured between VIH and VIL. 8) Measured with the specified current load and 100 pF at Vol = 0.8 V and Voh = 2.0 V. Access time is determined by the latter of t RAC, tCAC, tAA,tCPA. t CAC is measured from tristate. . 9) Operation within the tRCD (max.) limit ensures that tRAC (max.) can be met. tRCD (max.) is specified as a reference point only. If tRCD is greater than the specified tRCD (max.) limit, then access time is controlled by tCAC. 10) Operation within the tRAD (max.) limit ensures that tRAC (max.) can be met. tRAD (max.) is specified as a reference point only. If tRAD is greater than the specified tRAD (max.) limit, then access time is controlled by tAA. 11) Either tRCH or tRRH must be satisfied for a read cycle. 12) tOFF (max.) define the time at which the output achieves the open-circuit conditions and are not referenced to output voltage levels. tOFF is referenced from the rising edge of RAS or CAS, whichever occurs last. 13) tWCS is not a restrictive operating parameter. This is included in the data sheet as electrical characteristics only. If tWCS > tWCS (min.) , the cycle is an early write cycle and data out pin will remain open-circuit (high impedance) through the entire cycle. 14) These parameters are referenced to the CAS leading edge.
Semiconductor Group
9
HYM 322005S/GS-50/-60 2M x 32-Bit EDO-Module
L-SIM-72-10 Module package (single in-line memory module)
GLS58332
Semiconductor Group
10

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